The present invention relates to the field of network switches, and more particularly, to the storage of Management Information Based (MIB) objects related to the operation of a network switch.
A data network switch permits data communication among a plurality of media stations in a local area network. Data frames or packets, are transferred between stations by means of data network switch Media Access Controllers (MACs). The network switch passes data frames received from a transmitting station to a destination station based on the header information and the received data frame. Packet transmission events typically are tracked to provide a basis for statistical analysis of network operation with respect to each data network switch port. For example, the number of transmitted packets, received packets, transmissions collisions, and the like can be counted and polled periodically. These significant parameters, called xe2x80x9cobjectsxe2x80x9d, are collected in a Management Information Base (MIB). Through the use of statistical counters, determination can be made of improper device operations, such as, for example, loss of packets .
Conventionally, each MAC unit includes internal counters of limited capacity for counting a small number of MIB objects. Flip-flops are incremented each time an item is changed. The counted objects are output to readable registers. The increased MAC complexity owed to these components, coupled with a relatively limited MIB reporting functionality for this scheme, are significant disadvantages.
The implementation of MIB counters with flip-flops increases the size of the chip on which the network switch is implemented and therefore increases the cost of the chip. However, moving the storage of the MIB counters off-chip impacts the bandwidth of accesses to the memory. Furthermore, the operation of the MIB counters is significantly slowed by having to refer to the external memory with each operation involving the MIB counter.
Providing a random access based memory (RAM) on a network switch logic chip as a counter for MIB data received from all the MACs on the chip frees up the bandwidth memory and also allows the MIB counters to match speed with the on-chip MACs. A RAM based memory also reduces the costs of the chip in comparison to implementation of the MIB counters with flip-flops. However, the interfacing and operation of a RAM based MIB counter scheme conventionally requires a complicated arrangement to control read and write accesses to the MIB counters.
There is a need for a network switch that does not burden external memory bandwidth, and employs MIB counter control logic that is relatively less complex and ensures proper maintenance of the MIB counters.
This and other needs are met by embodiments of the present invention which provide a multiport network switch that maintains management information base (MIB) counters. The switch has a multiport random access memory which contains MIB counters at addressable locations in the memory. Read/write logic is coupled to the MIB counters to read and write specified MIB counters. The read/write logic includes a pipeline having an input that receives addresses of the MIB counter to be read or written.
In certain embodiments of the invention, control logic is provided that selectively prevents concurrent reading and writing of the same MIB counter. This allows a random access memory to be used, but at the same time prevents the reading of the MIB counter that is being updated. The pipeline is an elegant arrangement that is used in conjunction with the control logic to maintain the MIB counters on-chip and prevent the simultaneous reading and writing to the same address in the memory. Hence, some of the advantages of the present invention include fast access to the MIB counters, matching of the MIB counters to the speed of the MACs, (since the MIB counters may be located on the same chip as the MACs), and freeing up of the external memory bandwidth.
The earlier stated needs are met by another embodiment of the present invention which provides a MIB counter arrangement comprising a memory having MIB counters located at addresses in the memory, the memory being configured for simultaneous read and write accesses. A pipeline is provided having an input for receiving addresses and an output coupled to the memory for providing addresses to the memory. The pipeline has multiple stages for pipelining addresses received at the input. Control logic is provided for preventing simultaneous reading and writing to the same address in the memory.